How to Reduce Costs with Customized I/O on COTS FPGA Modules – 8500884

Reduce Costs with Customized I/O on COTS FPGA Modules

Reducing Costs with Customized I/O on COTS FPGA Modules

It is now common to deploy COTS FPGA modules to help speed development cycles and reduce overall project costs. However, to maximize savings when FPGAs are used to perform custom I/O functions, it is very important to first determine the suitability of a particular FPGA module for the application.

This determination is dependent upon several factors:

  1. The Size of the FPGA
  2. The Performance of the FPGA
  3. The I/O Interface of the FPGA Module

Acromag offers a broad family of FPGA modules to address the concerns of size and performance. But for this article, our discussion will focus on meeting the I/O interface requirements.

After selecting an FPGA module of sufficient resources, it is the I/O interface requirement that will determine whether the platform will solve the application at hand. As FPGA modules are more frequently used to build bridges between various sub-systems, it is necessary for an FPGA Analog Input: AXM-A30 TRANS-C5200 6U cPCI Transition Module providing Rear I/O through TTL Transceivers then to SCSI-3 Connectors CMOS & RS485 I/O: AXM-D03 module to quickly and easily adapt to the sub-system’s I/O interface requirements. Based upon experience in FPGA module applications, Acromag offers several standardized methods to customize the front and rear I/O interface on many of their PMC FPGA modules. A

Acromag’s Virtex-4 and Virtex-5 FPGA PMC modules feature both front and rear I/O. See Figure 1 below. Rear I/O consists of 64 I/O points accessible through the PMC JN4 connector. These I/O points are directly interfaced to the FPGA device and offer the configurability defined by the constraints file of the FPGA. Definable I/O types include: LVTTL, LVCMOS, LVDS, ELVDS, and Hyper-transport. Typically, rear I/O points are routed to the backplane. They are then routed through the backplane connector and can be used either directly as configured or further routed to a rear transition module (RTM) where additional signal conditioning may occur.

Click here to download complete PDF of How to Reduce Costs with Customized I/O on COTS FPGA Modules

More resources:

Acromag FPGA Products

PMC Modules for COTS and Industrial Projects

What is FPGA Zynq UltraScale+ with MPSoC? | Technology Paper

What are FPGAs and FPGA Applications? | Webcast Replay (part 1 of FPGA series)

How to Use Vivado for FPGA Modifications | Webcast Replay (Part 2 of FPGA series)

What is FPGA Zync UltraScale+? | Webcast Replay (Part 3 of FPGA series)


Would you like to have app notes like this delivered straight to your inbox? Click here to receive Acromag’s monthly eNewsletter.