How to Get the Timing Right in Critical FPGA Applications – 8400589
Get the Timing Right in Critical FPGA Applications
As the capacity of FPGA devices increases, the quantity and complexity of application tasks deployed on a single PMC FPGA module likewise increases. As a result, accurate management of all the unique clocks associated with these tasks becomes a very significant challenge for the application developer. In this article, we discuss the tools and constructs available to help an FPGA application designer get the timing right.
All logic executing within the fabric of an FPGA must be based upon one or more timeframe references more commonly called “clocks.” On the FPGA module, clocks are used to synchronize read/write operations, synchronize data transmission and capture, control the timing of data processing, and prepare data for storage. For example, it may take some multiple of 8 clock cycles to process and prepare a single 8-bit byte of data for storage in a memory device. To meet these needs, Acromag’s PMC FPGA modules include on-board crystal clocks for essential tasks such as driving the PCI-X bus and on-board memory devices. Acromag modules with Xilinx® Virtex-4® FPGAs have 200MHz and 66MHz crystals; modules with Virtex-5® FPGAs have 200MHz and 133MHz crystals. However, external clock lines are necessary when external signals require highly accurate synchronization for transmission or capture and processing.
Although any input point can be used as an external clock, some input points are specifically routed by Xilinx for low-skew, low-power operation to deliver low-jitter signals at high frequencies. Regional clock lines on Acromag’s Virtex-5 FPGA modules are routed to a specific clock region and its neighbors. The functional equivalents on Virtex-4 FPGA modules are called local clocks. Global clock lines are those routed for availability throughout the FPGA fabric.
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