XMC-7A50-AP323: XMC Module with Artix-7 FPGA and High-Density I/O

XMC-7A50-AP323: XMC Module with Artix-7 FPGA and High-Density I/O Description

XMC-7A51-AP323: 48 TTL channels

Custom Requirements: Other I/O combinations are possible, contact Acromag for more information.
Build Option A: 24 EIA-485/422 channels
Build Option B: 24 TTL and 12 EIA-485/422 channels
Build Option C: 24 LVDS channels

Designed for COTS applications, these XMC modules combine a user-customizable FPGA with digital I/O and high-performance analog inputs for high-density signal processing.

The XMC-7A50-AP323 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express. These XMC boards feature a best-in-class Artix®-7 interface to deliver the industry’s lowest power and high performance.

The analog inputs monitor 20 differential or 40 single-ended channels. Software or an external hardware input can trigger A/D conversions for synchronization to external events. On-board, precision voltage references enable accurate software calibration of the module without external instruments.

The Engineering Design Kit provides users with basic info. required to develop custom FPGA firmware for download to the Xilinx® FPGA. Example FPGA design code is provided as a Vivado IP Integrator project for functions such as a one-lane PCI Express interface, DMA, digital I/O control register, and more. Users should be fluent using Xilinx Vivado® design tools.

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XMC-7A50-AP323: XMC Module with Artix-7 FPGA and High-Density I/O Features & Benefits

Watch a quick overview video describing this module.

FPGA Digital I/O

• Reconfigurable Xilinx FPGA
• High channel count digital interface:
• TTL, RS485, and LVDS interface options
• 32Mb quad serial flash memory
• 52,160 logic cells
• 65,200 Flip flops
• 2,700 kb block RAM
• 120 DSP slices
• External LVTTL clock input
• Long distance data transmission
• Example design
• Power up and system reset is failsafe

Analog Input

• 20 differential or 40 single-ended inputs
• Flexible scan control
• 16-bit A/D resolution
• 8μs conversion time
• FIFO buffer with 16K sample memory
• Interrupt upon FIFIO threshold condition
• FIFO full, empty and threshold reached flags
• Programmable channel conversion control
• Programmable conversion timer
• Several scanning modes
• External trigger

General

• Wide temperature range
• Conduction cooling options
• Software development tools for VxWorks®, Linux®, and Windows® environments

Read the product release

Additional information