Click to zoom
$1,995$3,380

Please sign in or register to see model options and to add products to your cart.

Product short description:
  • Xilinx® Zynq UltraScale+ MPSoC
  • ARM Cortex™ A53 & R5 CPUs
  • Programmable logic
  • PCIe Bus Interface

APZU series modules provide a programmable Xilinx Zynq UltraScale+ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device.

Click here to watch a short video highlighting the features of the APZU Series.

 

APZU Series User Configurable Zynq UltraScale+ MPSoC Modules Description

AcroPack® modules are a ruggedized version of a mini PCIe card. AcroPacks add a down-facing 100-pin connector to internally route I/O signals through the carrier card to secure field connectors, thus eliminating loose cables and increasing reliability.

APZU modules provide a programmable Xilinx Zynq UltraScale+ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. Two dual-core ARM Cortex CPUs (A53 application processor and R5 real-time processor) deliver high-performance computation capability. Additional resources include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. The integrated ASIC-class programmable logic is ideal for compute-intensive tasks and offloading critical applications.

The real value of the Zynq UltraScale+ MPSoC architecture lies in the tight integration of its programmable logic with the processing system. Its high throughput interface eliminates bottlenecks that plague two-chip ASSP-FPGA solutions and allows designers to easily extend the processing system capabilities. Now developers can build custom designs by adding peripherals in the programmable logic and increase overall system performance by partitioning hardware and software functions with custom accelerators.

Designed for COTS applications these FPGA-based digital I/O modules deliver user-customizable I/O in a high-density and very rugged form factor. Typical applications involve adaptive filtering, sensor fusion, motor control, and image processing.

Acromag’s Engineering Design Kit (EDK) provides an FPGA generated firmware example design that provides host access to the hardware digital I/O on the APZU module. The example is implemented using the Xilinx Vivado® development environment and offers a starting point from which customers can develop their customized applications.

Performance Specifications

Multiprocessor SoC

MPSoC device: Xilinx Zynq XCZU3CG-2SBVA484I.
Application processor: Dual-core ARM Cortex-A53, 1.3GHz. Single/double precision floating point unit.
Real-time processor: Dual-core ARM Cortex-R5, 533MHz. Single/double precision floating point unit.
NEON Advanced SIMD media-processing engine.
Programmable logic resources: 154,350 logic cells; 70,560 LUTs; 360 DSP slices.
Configuration: Primary boot from SD card or NOR flash alternate.

I/O and Peripheral Interfaces

I/O connector: 68 pin field I/O (to carrier card).
Digital I/O: APZU-301: 28 TTL I/O channels (1.8V). APZU-303: 20 TTL and 3 RS485/422 channels (3.3V). APZU-304: 14 LVDS I/O channels.
Interrupts: 20 channels of interrupts configurable for high-to-low, low-to-high, and change-of-state event types.
LPDDR Memory: 2 Gbyte (512Mbit x 32).
Quad-SPI flash: 512 Mbit (64 Mbyte) Nor flash device.
SD card interface: 16 GB industrial MLC microSD card pre-programmed with boot.bin file.
Gigabit Ethernet interface: Supports 1000BASE-T, 100BASE-TX, and 10BASE-T. Zynq gigabit Ethernet controller uses a media independent interface (RGMII). External magnetics and RJ45 are provided on the breakout panel.
USB 2.0 interface: Microchip USB3320C.
UART to USB interface: Silicon Labs CP2103GM.
Breakout panel: Model 5028-626 panel mates directly to all 68-pin AcroPack carriers. Brings RJ45 ethernet port, USB 2.0 port, UART to USB port, digital I/O at jumper blocks, and power and reset buttons out to the field.

PCI Express

Compatibility: Conforms to PCI Express Base Specification, Rev.2.1.
PCIe interface: PCIe bus 1-lane (x1) Gen 1 interface. 2.5 Gbps signaling rate.
Memory space: 1M Byte: BAR0 to Zynq DMA registers. 32K Byte: BAR1 to programmable logic register space. 64K Byte: BAR2 to DDR memory space.

Environmental

Operating temperature: Air-cooled (with heat spreader): -40 to 70°C. (minimum airflow of 400LFM is recommended). Conduction-cooled: -40 to 80°C.
Storage temperature: -55 to 125°C .
Relative humidity: 5 to 95% non-condensing.
Power: 3.3V DC (±5%): 57 mA typical, 100 mA max. 5.0V DC (±5%): 183 mA typical, 230 mA max. +12V DC (±5%): 165 mA typical, 200 mA max. 1.5V, –12V DC: not used.
Vibration, sinusoidal operating: Designed to comply with IEC 60068-2-6. 10-500Hz, 5G, 2 hours/axis.
Vibration, random operating: Designed to comply with IEC 60068-2-64. 10-500Hz, 5G-rms, 2 hours/axis.
Shock, operating: Designed to comply with IEC 60068-2-27. 30G, 11ms half sine; 50G, 3mS half sine; 18 shocks at 6 orientations for both test levels.
Mean time between failure (MTBF): MIL-HDBK-217F, FN2. Ground benign, controlled.
25°C: 1,459,102 MTBF hours; 167 MTBF years; 685.4 failure rate (FIT).
40°C: 923,762 MTBF hours; 105.5 MTBF years; 1,082.5 failure rate (FIT).
FIT is failures in 109 hours.

Physical

Dimensions: Length, width, height: 70 x 30 x 12.5 mm.
Board thickness: 1.0 mm.
Weight: 35.18 g (including heat spreader).

Engineering Design Kit

Board support package and FPGA design kit for Xilinx Vivado®. Example of IP Block design, block RAM, system monitor, AXI interface to digital I/O.
Kit must be ordered with the first purchase of an APZU module.

 

 

Zynq MPSoC

  • Dual-core ARM Cortex A53-based application processor unit (APU)
  • Dual-core ARM Cortex R5-based real-time processor unit (RPU)
  • NEON™ media-processing engine
  • UltraScale+ 154k programmable logic cells
  • Extensive on-chip memory

I/O and Peripherals

  • TTL, LVDS, or RS422/485 I/O interface
  • Gigabit Ethernet interface
  • USB 2.0 transceiver
  • USB-UART debug terminal port

General

  • PCI Express interface
  • MicroSD or NOR flash boot
  • Quad-SPI flash memory
  • LPDDR4 storage memory
  • DMA transfers
  • BSP and FPGA design kit software
  • VxWorks®, Linux®, and Windows® support

 

 

 

 

 

What is FPGA Zynq UltraScale+?
APZU FPGA-based digital I/O modules provide programmable Xilinx® Zynq UltraScale+ MPSoC This paper is a brief overview of some of Acromag’s APZU FPGA Zynq® UltraScale+™ with MPSoC products, as well as the features of AcroPack Zinq UltraScale+, the carrier boards that host AcroPack mezzanine modules. We’ll highlight some of the development tools, the engineering design kit, and...
What are FPGAs and FPGA Applications? | Webcast
FPGAs and Their Use in the Embedded Space What are FPGAs and FPGA Applications in the Embedded Space? Topics in this webcast include: What FPGAs Are Best-suited Applications Coding Methods Processing Types This video is part one of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
How to Use Vivado for FPGA Modifications | Webcast
FPGA Design Modifications Using Vivado & Acromag Tools How to Use Vivado for FPGA Modifications. Topics in this webcast include: Vivado 2019.2 Acromag Example Design Compile Project Produce new MCS file This video is part two of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
What is FPGA Zync UltraScale+? | Webcast
These FPGA modules provide a programmable Xilinx Zynq® UltraScale+™ MPSoC What is FPGA Zync UltraScale+? Acromag’s APZU series modules provide a programmable Xilinx Zynq® UltraScale+™ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. The AcroPack® APZU Mini PCIe FPGA Series is the...
How do FPGA Modules Drive Real-Time Applications?
FPGA Modules with an Integrated Processor Drive Real-Time Applications Engineers developing DSP and high speed logic applications are now well-aware that FPGA modules can help them create an integrated, sophisticated solution. The availability of commercial off-the-shelf (COTS) FPGA boards can make these solutions viable and do so in reduced development times. Today, with systems architected...
Migrating from VME to VPX or PCIe: Top 6 Considerations | Webcast
In this webcast several important topics are covered for migrating from VME to VPX or PCIe. This includes the advantages and disadvantages of VME architecture, six key considerations, and an overview of migration to PCIe or VPX (advantages, disadvantages, complexity, performance and cost).   More Resources: What is FPGA Zynq UltraScale+ with MPSoC? | Technology...

Manuals

APZU AcroPack Series User Manual (Log in to download the file)

APZU PetaLinux User Manual (Log in to download the file)

APZU Cable Breakout User Manual (Log in to download the file)

Drawings & Diagrams

APSW-API-LNX (Log in to download the file)
  • Compare

    5028-626 Breakout Panel

    • Breakout panel for APZU series.
    • I/O breakout panel with cables for Ethernet, UART, JTAG, and 68-pin carrier card connections.
    $495
    Select options
  • Compare

    APSW-API: I/O Function Routines for VxWorks, Windows, Linux

    • Programming interface with function routines for AcroPack modules/carriers.
    • Customizable for other operating systems.
    $360$835
    Select options
  • Compare

    APZU-EDK: Engineering Design Kit

    Acromag’s Engineering Design Kit (EDK) provides an FPGA generated firmware example design that provides host access to the hardware digital I/O on the APZU module. The example is implemented using the Xilinx Vivado® development environment and offers a starting point from which customers can develop their customized applications.
    • CD containing
      • schematics
      • parts list
      • part location drawing
      • example Vivado and Vitis project files
      • other utility files.
    • One kit required
     
    $395
    Select options

Additional information

Weight 1.25 oz
Dimensions 3.25 × 1.25 × 1 in
FPGA Type

Zynq UltraScale+ MPSoC

Logic Cells

154k

Part Number

APZU-301: 28 TTL channels (1.8V)., APZU-303: 20 TTL & 3 EIA-485/422 channels (3.3V)., APZU-304: 14 LVDS channels., APZU-301-QSP: Quick Start Package

  • Description

    APZU Series User Configurable Zynq UltraScale+ MPSoC Modules Description

    AcroPack® modules are a ruggedized version of a mini PCIe card. AcroPacks add a down-facing 100-pin connector to internally route I/O signals through the carrier card to secure field connectors, thus eliminating loose cables and increasing reliability.

    APZU modules provide a programmable Xilinx Zynq UltraScale+ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. Two dual-core ARM Cortex CPUs (A53 application processor and R5 real-time processor) deliver high-performance computation capability. Additional resources include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. The integrated ASIC-class programmable logic is ideal for compute-intensive tasks and offloading critical applications.

    The real value of the Zynq UltraScale+ MPSoC architecture lies in the tight integration of its programmable logic with the processing system. Its high throughput interface eliminates bottlenecks that plague two-chip ASSP-FPGA solutions and allows designers to easily extend the processing system capabilities. Now developers can build custom designs by adding peripherals in the programmable logic and increase overall system performance by partitioning hardware and software functions with custom accelerators.

    Designed for COTS applications these FPGA-based digital I/O modules deliver user-customizable I/O in a high-density and very rugged form factor. Typical applications involve adaptive filtering, sensor fusion, motor control, and image processing.

    Acromag’s Engineering Design Kit (EDK) provides an FPGA generated firmware example design that provides host access to the hardware digital I/O on the APZU module. The example is implemented using the Xilinx Vivado® development environment and offers a starting point from which customers can develop their customized applications.

    Performance Specifications

    Multiprocessor SoC

    MPSoC device: Xilinx Zynq XCZU3CG-2SBVA484I.
    Application processor: Dual-core ARM Cortex-A53, 1.3GHz. Single/double precision floating point unit.
    Real-time processor: Dual-core ARM Cortex-R5, 533MHz. Single/double precision floating point unit.
    NEON Advanced SIMD media-processing engine.
    Programmable logic resources: 154,350 logic cells; 70,560 LUTs; 360 DSP slices.
    Configuration: Primary boot from SD card or NOR flash alternate.

    I/O and Peripheral Interfaces

    I/O connector: 68 pin field I/O (to carrier card).
    Digital I/O: APZU-301: 28 TTL I/O channels (1.8V). APZU-303: 20 TTL and 3 RS485/422 channels (3.3V). APZU-304: 14 LVDS I/O channels.
    Interrupts: 20 channels of interrupts configurable for high-to-low, low-to-high, and change-of-state event types.
    LPDDR Memory: 2 Gbyte (512Mbit x 32).
    Quad-SPI flash: 512 Mbit (64 Mbyte) Nor flash device.
    SD card interface: 16 GB industrial MLC microSD card pre-programmed with boot.bin file.
    Gigabit Ethernet interface: Supports 1000BASE-T, 100BASE-TX, and 10BASE-T. Zynq gigabit Ethernet controller uses a media independent interface (RGMII). External magnetics and RJ45 are provided on the breakout panel.
    USB 2.0 interface: Microchip USB3320C.
    UART to USB interface: Silicon Labs CP2103GM.
    Breakout panel: Model 5028-626 panel mates directly to all 68-pin AcroPack carriers. Brings RJ45 ethernet port, USB 2.0 port, UART to USB port, digital I/O at jumper blocks, and power and reset buttons out to the field.

    PCI Express

    Compatibility: Conforms to PCI Express Base Specification, Rev.2.1.
    PCIe interface: PCIe bus 1-lane (x1) Gen 1 interface. 2.5 Gbps signaling rate.
    Memory space: 1M Byte: BAR0 to Zynq DMA registers. 32K Byte: BAR1 to programmable logic register space. 64K Byte: BAR2 to DDR memory space.

    Environmental

    Operating temperature: Air-cooled (with heat spreader): -40 to 70°C. (minimum airflow of 400LFM is recommended). Conduction-cooled: -40 to 80°C.
    Storage temperature: -55 to 125°C .
    Relative humidity: 5 to 95% non-condensing.
    Power: 3.3V DC (±5%): 57 mA typical, 100 mA max. 5.0V DC (±5%): 183 mA typical, 230 mA max. +12V DC (±5%): 165 mA typical, 200 mA max. 1.5V, –12V DC: not used.
    Vibration, sinusoidal operating: Designed to comply with IEC 60068-2-6. 10-500Hz, 5G, 2 hours/axis.
    Vibration, random operating: Designed to comply with IEC 60068-2-64. 10-500Hz, 5G-rms, 2 hours/axis.
    Shock, operating: Designed to comply with IEC 60068-2-27. 30G, 11ms half sine; 50G, 3mS half sine; 18 shocks at 6 orientations for both test levels.
    Mean time between failure (MTBF): MIL-HDBK-217F, FN2. Ground benign, controlled.
    25°C: 1,459,102 MTBF hours; 167 MTBF years; 685.4 failure rate (FIT).
    40°C: 923,762 MTBF hours; 105.5 MTBF years; 1,082.5 failure rate (FIT).
    FIT is failures in 109 hours.

    Physical

    Dimensions: Length, width, height: 70 x 30 x 12.5 mm.
    Board thickness: 1.0 mm.
    Weight: 35.18 g (including heat spreader).

    Engineering Design Kit

    Board support package and FPGA design kit for Xilinx Vivado®. Example of IP Block design, block RAM, system monitor, AXI interface to digital I/O.
    Kit must be ordered with the first purchase of an APZU module.

     

     

  • Features & Benefits

    Zynq MPSoC

    • Dual-core ARM Cortex A53-based application processor unit (APU)
    • Dual-core ARM Cortex R5-based real-time processor unit (RPU)
    • NEON™ media-processing engine
    • UltraScale+ 154k programmable logic cells
    • Extensive on-chip memory

    I/O and Peripherals

    • TTL, LVDS, or RS422/485 I/O interface
    • Gigabit Ethernet interface
    • USB 2.0 transceiver
    • USB-UART debug terminal port

    General

    • PCI Express interface
    • MicroSD or NOR flash boot
    • Quad-SPI flash memory
    • LPDDR4 storage memory
    • DMA transfers
    • BSP and FPGA design kit software
    • VxWorks®, Linux®, and Windows® support

     

     

     

     

     

  • Tech Papers

    What is FPGA Zynq UltraScale+?
    APZU FPGA-based digital I/O modules provide programmable Xilinx® Zynq UltraScale+ MPSoC This paper is a brief overview of some of Acromag’s APZU FPGA Zynq® UltraScale+™ with MPSoC products, as well as the features of AcroPack Zinq UltraScale+, the carrier boards that host AcroPack mezzanine modules. We’ll highlight some of the development tools, the engineering design kit, and...
    What are FPGAs and FPGA Applications? | Webcast
    FPGAs and Their Use in the Embedded Space What are FPGAs and FPGA Applications in the Embedded Space? Topics in this webcast include: What FPGAs Are Best-suited Applications Coding Methods Processing Types This video is part one of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
    How to Use Vivado for FPGA Modifications | Webcast
    FPGA Design Modifications Using Vivado & Acromag Tools How to Use Vivado for FPGA Modifications. Topics in this webcast include: Vivado 2019.2 Acromag Example Design Compile Project Produce new MCS file This video is part two of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
    What is FPGA Zync UltraScale+? | Webcast
    These FPGA modules provide a programmable Xilinx Zynq® UltraScale+™ MPSoC What is FPGA Zync UltraScale+? Acromag’s APZU series modules provide a programmable Xilinx Zynq® UltraScale+™ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. The AcroPack® APZU Mini PCIe FPGA Series is the...
    How do FPGA Modules Drive Real-Time Applications?
    FPGA Modules with an Integrated Processor Drive Real-Time Applications Engineers developing DSP and high speed logic applications are now well-aware that FPGA modules can help them create an integrated, sophisticated solution. The availability of commercial off-the-shelf (COTS) FPGA boards can make these solutions viable and do so in reduced development times. Today, with systems architected...
    Migrating from VME to VPX or PCIe: Top 6 Considerations | Webcast
    In this webcast several important topics are covered for migrating from VME to VPX or PCIe. This includes the advantages and disadvantages of VME architecture, six key considerations, and an overview of migration to PCIe or VPX (advantages, disadvantages, complexity, performance and cost).   More Resources: What is FPGA Zynq UltraScale+ with MPSoC? | Technology...
  • Specs & Data Sheets

    Manuals

    APZU AcroPack Series User Manual (Log in to download the file)

    APZU PetaLinux User Manual (Log in to download the file)

    APZU Cable Breakout User Manual (Log in to download the file)

    Drawings & Diagrams

  • Software

    APSW-API-LNX (Log in to download the file)
  • Accessories

    • Compare

      5028-626 Breakout Panel

      • Breakout panel for APZU series.
      • I/O breakout panel with cables for Ethernet, UART, JTAG, and 68-pin carrier card connections.
      $495
      Select options
    • Compare

      APSW-API: I/O Function Routines for VxWorks, Windows, Linux

      • Programming interface with function routines for AcroPack modules/carriers.
      • Customizable for other operating systems.
      $360$835
      Select options
    • Compare

      APZU-EDK: Engineering Design Kit

      Acromag’s Engineering Design Kit (EDK) provides an FPGA generated firmware example design that provides host access to the hardware digital I/O on the APZU module. The example is implemented using the Xilinx Vivado® development environment and offers a starting point from which customers can develop their customized applications.
      • CD containing
        • schematics
        • parts list
        • part location drawing
        • example Vivado and Vitis project files
        • other utility files.
      • One kit required
       
      $395
      Select options
  • Additional information

    Additional information

    Weight 1.25 oz
    Dimensions 3.25 × 1.25 × 1 in
    FPGA Type

    Zynq UltraScale+ MPSoC

    Logic Cells

    154k

    Part Number

    APZU-301: 28 TTL channels (1.8V)., APZU-303: 20 TTL & 3 EIA-485/422 channels (3.3V)., APZU-304: 14 LVDS channels., APZU-301-QSP: Quick Start Package