Click to zoom

Please sign in or register to see model options and to add products to your cart.

Product short description:
  • 52,160 logic cells
  • Reconfigurable Xilinx Artix-7 FPGA
  • PCI Express bus interface
  • Conduction or air cooled

The APA7-500 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express.

Click here to watch a short video highlighting the features of Acromag’s APA7-500 Series.

The APA7-500 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express. These boards feature a best in class Artix-7 interface to deliver the industry’s lowest power and high performance.

Designed for COTS applications these FPGA based digital I/O modules deliver user-customizable I/O, high-density, high-reliability, and high-performance at a low cost.

The AcroPack® product line updates our popular Industry Pack I/O modules with a PCIe interface format. This tech-refresh design offers a compact size, low-cost I/O, the same functionality as the existing Industry Pack modules and a rugged form factor.

The APA7-500 series modules are 70mm long. This is 19.05mm longer than the full length mini PCIe card at 50.95mm. The boards width is the same as mPCIe board of 30mm and they use the same mPCIe standard board hold down standoff and screw keep out areas.

A down facing 100 pin Samtec connector mates with the carrier card. Fifty of these pins are available for field I/O signals.

The Engineering Design Kit provides users with basic information required to develop custom FPGA firmware for download to the Xilinx FPGA. Example FPGA design code is provided as a Vivado IP Integrator project for functions such as a one-lane PCI Express interface, DMA, digital I/O control register, and more. Users should be fluent in the use of Xilinx Vivado design tools.

Performance Specifications

FPGA

FPGA device: Xilinx Artix-7 FPGA Model XC7A50T
FPGA configuration: Download via flash memory
Example FPGA program: IP integrator block diagram provided for PCIe bus 1 lane Gen 1 interface, DMA controller, on chip block RAM, flash memory and control of field I/O. See EDK kit.

I/O Processing

Field I/O Interface: PCIe bus 1 lane Gen 1 interface
I/O Connector: 100 pin field I/O connector

Engineering Design Kit

Provides user with basic information required to develop a custom FPGA program. Kit must be ordered with the first purchase of a APA7-500 series module.

PCI Express Base Specification

Conforms to revision 2.0
Lanes: 1 lane in each direction
Bus Speed: 2.5 Gbps (Generation 1)
Memory: 128k space required. 1 base address register.

Environmental

Operating temperature:
Air Cooled with heat sink: -40 to 80°C
Air Cooled without heat sink: -40 to 70°C
Conduction Cooled: -40 to 85°C ( A conduction cooled application with an AcroPack requires heatsink model AP-CC-01.)
Storage temperature: -55 to 125°C
Relative humidity: 5 to 95% non-condensing
Power: 3.3V (±5%) 500mA typical

Physical

Length: 70mm.
Width: 30mm.

  • PCI Express Generation 1 interface
  • Reconfigurable Xilinx® FPGA
  • Mix and match countless I/O combinations in a single slot.
  • High channel count digital interface: RS485, LVDS and TTL interface options
  • 32Mb quad serial Flash memory
  • 52,160 logic cells
  • 65,200 Flip flops
  • 2,700 kb block RAM
  • 120 DSP slices
  • External LVTTL clock input
  • Long distance data transmission
  • Example design
  • Power up and systemd reset is failsafe
  • Conduction-cooled options
  • Solid-down connector I/O interface
  • Wide temperature range
  • VPX and PCIe carriers
  • Linux®, Windows®, and VxWorks® support
What is FPGA Zynq UltraScale+ with MPSoC? | Whitepaper (Log in to view the file)
APZU FPGA-based digital I/O modules provide programmable Xilinx® Zynq UltraScale+ MPSoC This paper is a brief overview of some of Acromag’s APZU FPGA Zynq® UltraScale+™ with MPSoC products, as well as the features of AcroPack Zinq UltraScale+, the carrier boards that host AcroPack mezzanine modules. We’ll highlight some of the development tools, the engineering design kit, and...
What are FPGAs and FPGA Applications? | Webcast
FPGAs and Their Use in the Embedded Space What are FPGAs and FPGA Applications in the Embedded Space? Topics in this webcast include: What FPGAs Are Best-suited Applications Coding Methods Processing Types This video is part one of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
How to Use Vivado for FPGA Modifications | Webcast
FPGA Design Modifications Using Vivado & Acromag Tools How to Use Vivado for FPGA Modifications. Topics in this webcast include: Vivado 2019.2 Acromag Example Design Compile Project Produce new MCS file This video is part two of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
What is FPGA Zync UltraScale+? | Webcast
These FPGA modules provide a programmable Xilinx Zynq® UltraScale+™ MPSoC What is FPGA Zync UltraScale+? Acromag’s APZU series modules provide a programmable Xilinx Zynq® UltraScale+™ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. The AcroPack® APZU Mini PCIe FPGA Series is the...
How do FPGA Modules Drive Real-Time Applications? - 8400-530
FPGA Modules with an Integrated Processor Drive Real-Time Applications Engineers developing DSP and high speed logic applications are now well-aware that FPGA modules can help them create an integrated, sophisticated solution. The availability of commercial off-the-shelf (COTS) FPGA boards can make these solutions viable and do so in reduced development times. Today, with systems architected...
Migrating from VME to VPX or PCIe: Top 6 Considerations | Webcast
In this webcast several important topics are covered for migrating from VME to VPX or PCIe. This includes the advantages and disadvantages of VME architecture, six key considerations, and an overview of migration to PCIe or VPX (advantages, disadvantages, complexity, performance and cost).   More Resources: What is FPGA Zynq UltraScale+ with MPSoC? | Technology...
APSW-API-LNX (Log in to download the file)

Additional information

Weight 0.8 oz
Dimensions 3.25 × 1.25 × 1 in
Part Number

APA7-501E-LF: 48 TTL channels, APA7-502E-LF: 24 RS485/422 channels, APA7-503E-LF: 24 TTL & 12 RS485/422 Channels, APA7-504E-LF: 24 LVDS channels

FPGA Type

Xilinx Artix-7

Logic Cells

52K

  • Description

    The APA7-500 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express. These boards feature a best in class Artix-7 interface to deliver the industry’s lowest power and high performance.

    Designed for COTS applications these FPGA based digital I/O modules deliver user-customizable I/O, high-density, high-reliability, and high-performance at a low cost.

    The AcroPack® product line updates our popular Industry Pack I/O modules with a PCIe interface format. This tech-refresh design offers a compact size, low-cost I/O, the same functionality as the existing Industry Pack modules and a rugged form factor.

    The APA7-500 series modules are 70mm long. This is 19.05mm longer than the full length mini PCIe card at 50.95mm. The boards width is the same as mPCIe board of 30mm and they use the same mPCIe standard board hold down standoff and screw keep out areas.

    A down facing 100 pin Samtec connector mates with the carrier card. Fifty of these pins are available for field I/O signals.

    The Engineering Design Kit provides users with basic information required to develop custom FPGA firmware for download to the Xilinx FPGA. Example FPGA design code is provided as a Vivado IP Integrator project for functions such as a one-lane PCI Express interface, DMA, digital I/O control register, and more. Users should be fluent in the use of Xilinx Vivado design tools.

    Performance Specifications

    FPGA

    FPGA device: Xilinx Artix-7 FPGA Model XC7A50T
    FPGA configuration: Download via flash memory
    Example FPGA program: IP integrator block diagram provided for PCIe bus 1 lane Gen 1 interface, DMA controller, on chip block RAM, flash memory and control of field I/O. See EDK kit.

    I/O Processing

    Field I/O Interface: PCIe bus 1 lane Gen 1 interface
    I/O Connector: 100 pin field I/O connector

    Engineering Design Kit

    Provides user with basic information required to develop a custom FPGA program. Kit must be ordered with the first purchase of a APA7-500 series module.

    PCI Express Base Specification

    Conforms to revision 2.0
    Lanes: 1 lane in each direction
    Bus Speed: 2.5 Gbps (Generation 1)
    Memory: 128k space required. 1 base address register.

    Environmental

    Operating temperature:
    Air Cooled with heat sink: -40 to 80°C
    Air Cooled without heat sink: -40 to 70°C
    Conduction Cooled: -40 to 85°C ( A conduction cooled application with an AcroPack requires heatsink model AP-CC-01.)
    Storage temperature: -55 to 125°C
    Relative humidity: 5 to 95% non-condensing
    Power: 3.3V (±5%) 500mA typical

    Physical

    Length: 70mm.
    Width: 30mm.

  • Features & Benefits

    • PCI Express Generation 1 interface
    • Reconfigurable Xilinx® FPGA
    • Mix and match countless I/O combinations in a single slot.
    • High channel count digital interface: RS485, LVDS and TTL interface options
    • 32Mb quad serial Flash memory
    • 52,160 logic cells
    • 65,200 Flip flops
    • 2,700 kb block RAM
    • 120 DSP slices
    • External LVTTL clock input
    • Long distance data transmission
    • Example design
    • Power up and systemd reset is failsafe
    • Conduction-cooled options
    • Solid-down connector I/O interface
    • Wide temperature range
    • VPX and PCIe carriers
    • Linux®, Windows®, and VxWorks® support
  • Tech Papers

    What is FPGA Zynq UltraScale+ with MPSoC? | Whitepaper (Log in to view the file)
    APZU FPGA-based digital I/O modules provide programmable Xilinx® Zynq UltraScale+ MPSoC This paper is a brief overview of some of Acromag’s APZU FPGA Zynq® UltraScale+™ with MPSoC products, as well as the features of AcroPack Zinq UltraScale+, the carrier boards that host AcroPack mezzanine modules. We’ll highlight some of the development tools, the engineering design kit, and...
    What are FPGAs and FPGA Applications? | Webcast
    FPGAs and Their Use in the Embedded Space What are FPGAs and FPGA Applications in the Embedded Space? Topics in this webcast include: What FPGAs Are Best-suited Applications Coding Methods Processing Types This video is part one of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
    How to Use Vivado for FPGA Modifications | Webcast
    FPGA Design Modifications Using Vivado & Acromag Tools How to Use Vivado for FPGA Modifications. Topics in this webcast include: Vivado 2019.2 Acromag Example Design Compile Project Produce new MCS file This video is part two of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
    What is FPGA Zync UltraScale+? | Webcast
    These FPGA modules provide a programmable Xilinx Zynq® UltraScale+™ MPSoC What is FPGA Zync UltraScale+? Acromag’s APZU series modules provide a programmable Xilinx Zynq® UltraScale+™ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. The AcroPack® APZU Mini PCIe FPGA Series is the...
    How do FPGA Modules Drive Real-Time Applications? - 8400-530
    FPGA Modules with an Integrated Processor Drive Real-Time Applications Engineers developing DSP and high speed logic applications are now well-aware that FPGA modules can help them create an integrated, sophisticated solution. The availability of commercial off-the-shelf (COTS) FPGA boards can make these solutions viable and do so in reduced development times. Today, with systems architected...
    Migrating from VME to VPX or PCIe: Top 6 Considerations | Webcast
    In this webcast several important topics are covered for migrating from VME to VPX or PCIe. This includes the advantages and disadvantages of VME architecture, six key considerations, and an overview of migration to PCIe or VPX (advantages, disadvantages, complexity, performance and cost).   More Resources: What is FPGA Zynq UltraScale+ with MPSoC? | Technology...
  • Specs & Data Sheets

  • Software

    APSW-API-LNX (Log in to download the file)
  • Accessories

  • Additional information

    Additional information

    Weight 0.8 oz
    Dimensions 3.25 × 1.25 × 1 in
    Part Number

    APA7-501E-LF: 48 TTL channels, APA7-502E-LF: 24 RS485/422 channels, APA7-503E-LF: 24 TTL & 12 RS485/422 Channels, APA7-504E-LF: 24 LVDS channels

    FPGA Type

    Xilinx Artix-7

    Logic Cells

    52K