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Product short description:
  • One or two 1553 interface channels
  • DDC Micro-ACE controls 1553 interface
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IP570 modules offer a choice of one or two channels to interface sensors and other devices to a 1553 bus.

MIL-STD-1553 (1553) is a digital internal time division command/response multiplex data bus. It is a military standard which has become one of the basic tools used by the U.S. Department of Defense for integration of weapon systems. MIL-STD-1553 describes the method of communication and the electrical interface requirements for subsystems connected to the data bus. Since its introduction, MIL-STD-1553 applications have extended to systems integration of flight controls, propulsion controls, and vehicle management (electrical, hydraulic, environmental control, etc.).

MIL-STD-1553 is designed for use in one of three forms:

Bus Controller (BC) – There is only one Bus Controller at a time on any MIL-STD-1553 bus. It initiates all message communication over the bus.

Remote Terminal (RT) – Up to 31 remote terminals can be present in the system.

Bus Monitor (BM) – A Bus Monitor cannot transmit messages over the data bus. Its primary role is to monitor and record bus transactions without interfering with operation of the Bus Controller or the Remote Terminals. Bus Monitor is often configured to record a subset of the transactions, based on criteria provided by the application program.

MIL-STD-1553 is ideal for these applications:

  • Missile system testing
  • Air traffic control system testing
  • On-board aircraft system monitoring
  • Satellite test systems
  • Aircraft simulators

Performance Specifications

MIL-STD-1553 Bus

Configuration: One or two dual-redundant MIL-STD-1553 Rev. A/B. Notice 2 bus interface channels.
Data memory: 64K RAM per channel.
Maximum data rate: 1MHz.

IP Compliance (ANSI/VITA 4)

Meets IP specifications per ANSI/VITA 4-1995 (R2002).
Data transfer cycle types supported:
Input/output (IOSel*), ID read (IDSel*), Interrupt Select (INTSel*), Memory (MEMSel*).
Access times (8MHz clock)
ID PROM Read: 1 wait state (375nS cycle).
I/O Space Read: 1 wait state (375nS cycle).
I/O Space Write: 0 wait state (250nS cycle).
Interrupt Select Read: 1 wait state (375nS cycle).
Memory Space Read: 3 wait state (750nS cycle).
Memory Space Write: 1 wait state (375nS cycle).
Access times (32MHz clock)
ID PROM Read: 1 wait state (94nS cycle).
I/O Space Read: 1 wait state (94nS cycle).
I/O Space Write: 0 wait state (63nS cycle).
Interrupt Select Read: 1 wait state (94nS cycle).
Memory Space Read: 9 wait state (344nS cycle).
Memory Space Write: 8 wait state (313nS cycle).

Engineering Design Kit
Provides user with basic information required to develop a custom FPGA program. Kit must be ordered with the first purchase.

Environmental

Operating temperature: 0 to 70°C or -40 to 85°C (E models).
Storage temperature: -55 to 125°C.
Relative humidity: 5 to 95% non-condensing.
Power:
IP571
+5V: 0.3A typical, 0.6A maximum.
+12V: 0A maximum.
–12V: 0A maximum.
IP572
+5V: 0.6A typical, 1.2A maximum.
+12V: 0A maximum.
–12V: 0A maximum.
MTBF: Contact the factory.

  • One or two complete dual-redundant MIL-STD-1553 bus interfaces
  • Supports both MIL-STD-1553 revision B and MIL-STD-1760 transceivers
  • All channels are transformer coupled
  • Data rates of up to 1Mb/s
  • Supports both 8 MHz and 32MHz IP operation
  • DDC Micro-ACE controls 1553 interface
    • Fully integrates 1553 Rev A/B Notice 2 terminal
    • Supports transceiver power-down options
    • Supports enhanced Mini-ACE architecture
    • Supports multiple configurations with 64K RAM: bus controller, remote terminal, or bus monitor
    • Supports 1553 Rev A/B Notice 2 and STANAG 3838 protocols
    • MIL-STD-1760 amplitude compliant transceiver
    • Provides highly flexible host-side interface
    • Compatible with Mini-ACE and ACE
    • Provides highly autonomous bus controller with built-in message sequence controller
    • Offers choice of single, dual, and circular remote terminal buffering options
    • Provides selective message monitor
    • Includes comprehensive built-In self-test
    • 16MHz clock
    • Software libraries and drivers available for Windows® 2000/XP/Vista/7 (32-bit), VxWorks® and Linux

Manuals

IP570 User Manual (Log in to download the file)

Drawings & Diagrams

IPSW-API-LNX (Log in to download the file)

Additional information

Weight N/A
Dimensions 5 × 5 × 1 in
Part Number

IP-IOS570-EDK: Engineering design kit

  • Description

    Contains 1553 library to allow interface to standard Acromag drives.

  • Features & Benefits

    • One or two complete dual-redundant MIL-STD-1553 bus interfaces
    • Supports both MIL-STD-1553 revision B and MIL-STD-1760 transceivers
    • All channels are transformer coupled
    • Data rates of up to 1Mb/s
    • Supports both 8 MHz and 32MHz IP operation
    • DDC Micro-ACE controls 1553 interface
      • Fully integrates 1553 Rev A/B Notice 2 terminal
      • Supports transceiver power-down options
      • Supports enhanced Mini-ACE architecture
      • Supports multiple configurations with 64K RAM: bus controller, remote terminal, or bus monitor
      • Supports 1553 Rev A/B Notice 2 and STANAG 3838 protocols
      • MIL-STD-1760 amplitude compliant transceiver
      • Provides highly flexible host-side interface
      • Compatible with Mini-ACE and ACE
      • Provides highly autonomous bus controller with built-in message sequence controller
      • Offers choice of single, dual, and circular remote terminal buffering options
      • Provides selective message monitor
      • Includes comprehensive built-In self-test
      • 16MHz clock
      • Software libraries and drivers available for Windows® 2000/XP/Vista/7 (32-bit), VxWorks® and Linux
  • Specs & Data Sheets

    Manuals

    IP570 User Manual (Log in to download the file)

    Drawings & Diagrams

  • Software

    IPSW-API-LNX (Log in to download the file)
  • Accessories

  • Additional information

    Additional information

    Weight N/A
    Dimensions 5 × 5 × 1 in
    Part Number

    IP-IOS570-EDK: Engineering design kit