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Product short description:
  • Up to 48 TTL or 24 differential RS485
  • Altera Cyclone II EP2C20 FPGA programmable via JTAG port or via the IP bus directly

This series of plug-in mezzanine modules provides a user-customizable Altera® Cyclone II FPGA on an Industry Pack (IP) module. The module allows users to develop and store their own instruction set in the FPGA for adaptive computing applications.

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Typical uses include specialized communication systems over RS422/485 networks, test fixture simulation of signals over TTL-switched lines, and analysis of acquired data using specialized mathematical formulas such as those developed with MathWorks’s MatLab® software.

The FPGA on Acromag’s IP-EP200 modules can control up to 48 TTL or 24 RS485 I/O signals or a mix of both types. Another model interfaces 24 LVDS I/O channels. User application programs are downloaded through the JTAG port or via the IP bus directly into the FPGA. A pre-programmed internal CPLD facilitates initialization by acting as the bus controller during power-up and while the program is downloading. This bus controller is limited to functions necessary for power-up and downloading. After the program downloads, the FPGA takes control of the IP bus and the CPLD disables.

Watch: FPGA Computing for Speed and Flexibility

 

  • Altera Cyclone II EP2C20 FPGA
  • Four models available:
    • IP-EP201: 48 TTL I/O lines
    • IP-EP202: 24 differential RS485 I/O lines
    • IP-EP203: 24 TTL and 12 RS485 I/O lines
    • IP-EP204: 24 LVDS I/O lines
  • FPGA programmable via JTAG port or IP bus
  • Local static RAM (64K x 16) under FPGA control
  • LVTTL external clock connected directly to the FPGA
  • Supports 8MHz and 32MHz IP bus
  • Programmable PLL-based clock synthesizer
  • Example FPGA design code provided as VHDL
    • -8MHz IP bus interface
    •  Digital I/O control register
    •  others
  • Hardware support for DMA and memory space
  • 0 to 70°C (-40 to 85°C E models)

Manuals

IP-EP200 User Manual (Log in to download the file)

IP-EP-EDK Programming Guide (Log in to download the file)

Drawings & Diagrams

Additional information

Weight N/A
Dimensions N/A
Part Number

IP-EP201: 48 TTL bidirectional I/O., IP-EP201E: 48 TTL bidirectional I/O, extended temp. range., IP-EP202: 24 EIA-485 differential I/O., IP-EP202E: 24 EIA-485 differential I/O, extended temp. range., IP-EP203: 24 TTL and 12 EIA-485 differential I/O., IP-EP203E: 24 TTL and 12 EIA-485 differential I/O, extended temp. range., IP-EP204: 24 LVDS differential I/O., IP-EP204E: 24 LVDS differential I/O, extended temp. range.

FPGA Type

Altera Cyclone II

Product Series

Cyclone II Series

  • Description

    Typical uses include specialized communication systems over RS422/485 networks, test fixture simulation of signals over TTL-switched lines, and analysis of acquired data using specialized mathematical formulas such as those developed with MathWorks’s MatLab® software.

    The FPGA on Acromag’s IP-EP200 modules can control up to 48 TTL or 24 RS485 I/O signals or a mix of both types. Another model interfaces 24 LVDS I/O channels. User application programs are downloaded through the JTAG port or via the IP bus directly into the FPGA. A pre-programmed internal CPLD facilitates initialization by acting as the bus controller during power-up and while the program is downloading. This bus controller is limited to functions necessary for power-up and downloading. After the program downloads, the FPGA takes control of the IP bus and the CPLD disables.

    Watch: FPGA Computing for Speed and Flexibility

     

  • Features & Benefits

    • Altera Cyclone II EP2C20 FPGA
    • Four models available:
      • IP-EP201: 48 TTL I/O lines
      • IP-EP202: 24 differential RS485 I/O lines
      • IP-EP203: 24 TTL and 12 RS485 I/O lines
      • IP-EP204: 24 LVDS I/O lines
    • FPGA programmable via JTAG port or IP bus
    • Local static RAM (64K x 16) under FPGA control
    • LVTTL external clock connected directly to the FPGA
    • Supports 8MHz and 32MHz IP bus
    • Programmable PLL-based clock synthesizer
    • Example FPGA design code provided as VHDL
      • -8MHz IP bus interface
      •  Digital I/O control register
      •  others
    • Hardware support for DMA and memory space
    • 0 to 70°C (-40 to 85°C E models)
  • Specs & Data Sheets

    Manuals

    IP-EP200 User Manual (Log in to download the file)

    IP-EP-EDK Programming Guide (Log in to download the file)

    Drawings & Diagrams

  • Additional information

    Additional information

    Weight N/A
    Dimensions N/A
    Part Number

    IP-EP201: 48 TTL bidirectional I/O., IP-EP201E: 48 TTL bidirectional I/O, extended temp. range., IP-EP202: 24 EIA-485 differential I/O., IP-EP202E: 24 EIA-485 differential I/O, extended temp. range., IP-EP203: 24 TTL and 12 EIA-485 differential I/O., IP-EP203E: 24 TTL and 12 EIA-485 differential I/O, extended temp. range., IP-EP204: 24 LVDS differential I/O., IP-EP204E: 24 LVDS differential I/O, extended temp. range.

    FPGA Type

    Altera Cyclone II

    Product Series

    Cyclone II Series