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Product short description:
  • Holds two PMC/XMC modules
  • PCIe bus 16-lane Gen 1 or 2 interface switch on data plane
  • Air-cooled and conduction-cooled versions

The VPX4821A carrier card provides a simple and cost-effective solution for interfacing a PMC or XMC module to a VPX computer system.

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Connect to the OpenVPX™ via Data plane for a direct PCIe connection over the VPX backplane. This allows host processors access to a high-performance, low latency interconnect to the PMC and XMC modules on the carrier card.

The PMC site uses 32/64-bit, PLX technology with a PCIe to PCI-X bridge; while the XMC site enables rapid data throughput with its use of an 8-lane PCIe Gen 2 interface. These sites support front or rear panel I/O.

By inserting PMC or XMC industrial I/O and configurable FPGA modules, developers can now leverage hundreds of available functions currently unavailable in a VPX platform.

These carriers are ideal for high-performance industrial, defense, scientific research, and telephony systems requiring high-speed I/O expansion. The VPX4821A is available in two versions: air-cooled and conduction-cooled.

The VPX4821A is one member of a family of 3U and 6U OpenVPX mezzanine carrier cards that support a simple and cost-effective solution for interfacing XMC or PMC modules to OpenVPX computer systems.

Performance Specifications

General

Form Factor: 6U VPX bus 6.299” (160mm) x 9.173” (233.0mm).

Pitch: VPX4821A (air-cooled): 1.0” pitch. VPX4821A-CC (conduction-cooled): 0.81” pitch.

Front Panel: The VPX4821A-LF has a 1.0” VITA 48.1 front panel. Contact the factory for IEEE 1101.10 1.0” and 0.8” options.

VPX Carrier Interface: Compatible VITA 65 module / slot profiles:

Data Plane PCIe Gen 1: MOD6-PER-4F-12.3.1-2, MOD6-PER-2F-12.3.2-1, MOD6-PER-1U-12.3.3-1, MOD6-PER-1F-12.3.4-1

Data Plane PCIe Gen 2:MOD6-PER-4F-12.3.1-3, MOD6-PER-2F-12.3.2-2, MOD6-PER-1U-12.3.3-2, MOD6-PER-1F-12.3.4-2

Note 1: Board is compatible with payload profiles but has no hosting capabilities.

FRU EEPROM with temperature monitor.

PMC/XMC Interface: Two IEEE 1386-2001 PMC/XMC modules in a single VPX slot.

PMC site is PCI-X 2.0 compliant, 32/64-bit, 33/66/133MHz, up to 1GB/s.

XMC site is PCIe Gen 2 and 8 lanes wide.

Front panel I/O support for the PMC/XMC site with 32 differential pairs (air cooled only).

Rear I/O support for the PMC site with 64 I/O lines.

Rear I/O support for XMC site with 20 differential pairs.

VITA 46.9 compliance: Slot 1 rear I/O map is P3w1-P64s+P4w1-X12d+X8d. Slot 2 rear I/O map is P5w1-P64s+P6w1-X12d+X8d.

Power

Power Requirements:

+5V DC (0 to 70°C): 8A maximum generated from +12V supply.

+5V DC (-40 to 85°C): 5A maximum generated from +12V supply.

+3.3V DC (0 to 70°C):8A maximum generated from +12V supply.

+3.3V DC (-40 to 85°C): 5A maximum generated from +12V supply.

+3.3V Aux DC: 5mA typical.

+12V DC and –12V DC provided to PMC site from VPX backplane.

+12V DC: Backplane voltage provided to XMC.

±12V Aux DC.

Note: see manual for further information.

Environmental

Air-Cooled Operating Temperature: 0 to 70°C (air flow requirement as measured to be greater than 200 LFM).

Conduction-Cooled Operating Temperature Range: -40 to 85°C (board must operate in a fully-installed conduction-cooled rack).

Storage Temperature Range: -55 to 100°C.

Relative Humidity: 5 to 95% non-condensing.

Weight: VPX4821A-LF: 1.25 lbs (0.5669kb). VPX4821A-CC-LF: 1.5 lbs (0.680kg)

Dimensions: Length: 10in, Height: 6.5in, Width: 1in

  • Connects to OpenVPX™ via Data plane
  • Support for upstream/downstream
  • Optional backplane configuration for one 16-lane port, two 8-lane ports, or four 4-lane ports
  • Supports dual standard (IEEE 1386.1) PMC/XMC modules with 25W mezzanine sites
  • PMC site uses 32/64-bit, 33/66/133MHz PLX technology with a PCIe to PCI-X bridge
  • Supports 64-bits of PMC I/O including differential routing to backplace per pattern “P64s” of VITA 46.9
  • 5V tolerant with respect to PMC connectors
  • XMC site uses PCIe x8 Gen 1 or 2 interface
  • Supports 40-bits (20 pairs) of XMC I/O to backplane per pattern “X12d+X8d” of VITA 46.9
  • Conforms to VITA 46.0, 46.4, 46.9
  • Supports front or rear panel PMC/XMC I/O
  • ±12V AUX power to PMC/XMC site
  • Monitors FRU information and module temperature

Manuals

VPX4821A User Manual (Log in to download the file)

Drawings & Diagrams

Additional information

Weight N/A
Dimensions N/A
Part Number

VPX4821A-42-LF: Air-cooled carrier, Data Plane with VITA 42, VPX4821A-42-CC-LF: Conduction-cooled carrier, Data Plane with VITA 42, VPX4821A-61-LF: Air-cooled carrier, Data Plane with VITA 61, VPX4821A-61-CC-LF: Conduction-cooled carrier, Data Plane with VITA 61

  • Description

    Connect to the OpenVPX™ via Data plane for a direct PCIe connection over the VPX backplane. This allows host processors access to a high-performance, low latency interconnect to the PMC and XMC modules on the carrier card.

    The PMC site uses 32/64-bit, PLX technology with a PCIe to PCI-X bridge; while the XMC site enables rapid data throughput with its use of an 8-lane PCIe Gen 2 interface. These sites support front or rear panel I/O.

    By inserting PMC or XMC industrial I/O and configurable FPGA modules, developers can now leverage hundreds of available functions currently unavailable in a VPX platform.

    These carriers are ideal for high-performance industrial, defense, scientific research, and telephony systems requiring high-speed I/O expansion. The VPX4821A is available in two versions: air-cooled and conduction-cooled.

    The VPX4821A is one member of a family of 3U and 6U OpenVPX mezzanine carrier cards that support a simple and cost-effective solution for interfacing XMC or PMC modules to OpenVPX computer systems.

    Performance Specifications

    General

    Form Factor: 6U VPX bus 6.299” (160mm) x 9.173” (233.0mm).

    Pitch: VPX4821A (air-cooled): 1.0” pitch. VPX4821A-CC (conduction-cooled): 0.81” pitch.

    Front Panel: The VPX4821A-LF has a 1.0” VITA 48.1 front panel. Contact the factory for IEEE 1101.10 1.0” and 0.8” options.

    VPX Carrier Interface: Compatible VITA 65 module / slot profiles:

    Data Plane PCIe Gen 1: MOD6-PER-4F-12.3.1-2, MOD6-PER-2F-12.3.2-1, MOD6-PER-1U-12.3.3-1, MOD6-PER-1F-12.3.4-1

    Data Plane PCIe Gen 2:MOD6-PER-4F-12.3.1-3, MOD6-PER-2F-12.3.2-2, MOD6-PER-1U-12.3.3-2, MOD6-PER-1F-12.3.4-2

    Note 1: Board is compatible with payload profiles but has no hosting capabilities.

    FRU EEPROM with temperature monitor.

    PMC/XMC Interface: Two IEEE 1386-2001 PMC/XMC modules in a single VPX slot.

    PMC site is PCI-X 2.0 compliant, 32/64-bit, 33/66/133MHz, up to 1GB/s.

    XMC site is PCIe Gen 2 and 8 lanes wide.

    Front panel I/O support for the PMC/XMC site with 32 differential pairs (air cooled only).

    Rear I/O support for the PMC site with 64 I/O lines.

    Rear I/O support for XMC site with 20 differential pairs.

    VITA 46.9 compliance: Slot 1 rear I/O map is P3w1-P64s+P4w1-X12d+X8d. Slot 2 rear I/O map is P5w1-P64s+P6w1-X12d+X8d.

    Power

    Power Requirements:

    +5V DC (0 to 70°C): 8A maximum generated from +12V supply.

    +5V DC (-40 to 85°C): 5A maximum generated from +12V supply.

    +3.3V DC (0 to 70°C):8A maximum generated from +12V supply.

    +3.3V DC (-40 to 85°C): 5A maximum generated from +12V supply.

    +3.3V Aux DC: 5mA typical.

    +12V DC and –12V DC provided to PMC site from VPX backplane.

    +12V DC: Backplane voltage provided to XMC.

    ±12V Aux DC.

    Note: see manual for further information.

    Environmental

    Air-Cooled Operating Temperature: 0 to 70°C (air flow requirement as measured to be greater than 200 LFM).

    Conduction-Cooled Operating Temperature Range: -40 to 85°C (board must operate in a fully-installed conduction-cooled rack).

    Storage Temperature Range: -55 to 100°C.

    Relative Humidity: 5 to 95% non-condensing.

    Weight: VPX4821A-LF: 1.25 lbs (0.5669kb). VPX4821A-CC-LF: 1.5 lbs (0.680kg)

    Dimensions: Length: 10in, Height: 6.5in, Width: 1in

  • Features & Benefits

    • Connects to OpenVPX™ via Data plane
    • Support for upstream/downstream
    • Optional backplane configuration for one 16-lane port, two 8-lane ports, or four 4-lane ports
    • Supports dual standard (IEEE 1386.1) PMC/XMC modules with 25W mezzanine sites
    • PMC site uses 32/64-bit, 33/66/133MHz PLX technology with a PCIe to PCI-X bridge
    • Supports 64-bits of PMC I/O including differential routing to backplace per pattern “P64s” of VITA 46.9
    • 5V tolerant with respect to PMC connectors
    • XMC site uses PCIe x8 Gen 1 or 2 interface
    • Supports 40-bits (20 pairs) of XMC I/O to backplane per pattern “X12d+X8d” of VITA 46.9
    • Conforms to VITA 46.0, 46.4, 46.9
    • Supports front or rear panel PMC/XMC I/O
    • ±12V AUX power to PMC/XMC site
    • Monitors FRU information and module temperature
  • Specs & Data Sheets

    Manuals

    VPX4821A User Manual (Log in to download the file)

    Drawings & Diagrams

  • Additional information

    Additional information

    Weight N/A
    Dimensions N/A
    Part Number

    VPX4821A-42-LF: Air-cooled carrier, Data Plane with VITA 42, VPX4821A-42-CC-LF: Conduction-cooled carrier, Data Plane with VITA 42, VPX4821A-61-LF: Air-cooled carrier, Data Plane with VITA 61, VPX4821A-61-CC-LF: Conduction-cooled carrier, Data Plane with VITA 61