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Product short description:
  • PCIe x16 Gen 3 interface via Data plane
  • One XMC and Four AcroPack slots
  • 6U form factor

The VPX4521 carrier card provides a simple and cost-effective solution for interfacing one XMC and four AcroPack modules to a VPX computer system.

Click here to watch a short AcroMaggie video highlighting the VPX4521 features.

 

 

VPX4521: VPX Carrier Card for AcroPack Modules Description

The VPX4521 carrier card provides a simple and cost-effective solution for interfacing one XMC and four AcroPack modules to a VPX computer system.

Connect to the OpenVPX™ compatible system via Data plane for a direct PCIe connection over the VPX backplane. This allows host processors access to a high-performance, low latency interconnect to the AcroPack and XMC modules on the carrier card.

By inserting AcroPack or XMC industrial I/O and configurable FPGA modules, developers can now leverage hundreds of available functions currently unavailable in a VPX platform.

These carriers are ideal for high-performance industrial, defense, scientific research, and telephony systems requiring high-speed I/O expansion. The VPX4521 is available in two versions: air-cooled and conduction-cooled.

The VPX4521 is a member of a 6U OpenVPX mezzanine carrier card family that supports a simple and cost-effective solution for interfacing XMC or AcroPack modules to OpenVPX computer systems.

Performance Specifications

NOTE: Specifications below only for VPX4521 carrier. See AcroPack and XMC data sheets for additional specifications.

PCI Express Bus Compliance

This device meets or exceeds all written PCI Express Base specifications per revision 3.1.
Includes a PCIe Gen 3 capable PCIe switch used to expand backplane PCIe port to multiple ports supporting various expansion cards. (AcroPack or mini-PCIe).
Downstream PCIe switch used to provide four one-lane PCIe ports to AcroPack devices.

Ease of Use

A unique carrier and site number is set via slot address. This provides the capability to distinguish a particular AcroPack module from others when multiple instances of the same module are used in a system.

A standard 14-pin Xilinx JTAG programming header is provided for programming and debugging the FPGA on some AcroPack modules. The JTAG ports of the four AcroPack modules are daisy-chained together.

There is a separate 14-pin Xilinx JTAG header provided for accessing devices on an XMC mezzanine module.

General

Form Factor: 6U VPX bus 6.299” (160mm) x 9.173” (233.0mm).

Pitch: 1”

VPX Carrier Interface: Compatible VITA 65 module / slot profiles: MOD6-PER-4F-12.3.1-n Data Plane PCIe Gen1/2/3. FRU EEPROM with temperature monitor.

Mezzanine Sites: One VITA 42 or VITA 61 XMC module.
XMC site is PCIe Gen 3 and 8 lanes wide.
Front panel I/O support for each AcroPack site with 68-pin CHAMP connector (air-cooled only).
Front panel I/O support for XMC module (air-cooled only).
Rear I/O support for the AcroPack site with 50 I/O lines.(conduction-cooled only).
XMC rear I/O compliance is P3w3-X38s+P4w1-X12d+x8d.

Power Requirements

Power for Carrier Board Only: +12V (VS1) – 0.9A typical, 1.5A maximum.

Environmental

Air-Cooled Operating Temperature: Standard models: 0 to 70°C. Extended temperature models: -40 to 85°C.

Conduction-Cooled Operating Temperature Range: -40 to 85°C (board must operate in a fully-installed conduction-cooled rack).

Storage Temperature Range: -55 to 125°C.

Relative Humidity: 5 to 95% non-condensing.

Vibration: Designed to comply with VITA 47 Class V1.

Shock: Designed to comply with VITA 47 Class OS1.

 

  • OpenVPX™ compatible via expansion plane connection
  • Support upstream/downstream PCIe links
  • Supports use of prXMC single board computers
  • Optional backplane configuration for one 16-lane port, two 8-lane ports, or four 4-lane ports
  • Supports standard VITA 42 and rugged VITA 61 XMC modules on 25W mezzanine site
  • XMC site supports PCIe x8 Gen 3 interface
  • 68 pin HD CHAMP front I/O connectors
  • Supports 78-bits (39 pairs) of XMC I/O to backplane per pattern X38s+X8d+X12d of VITA 46.9
  • Conforms to VITA 42.0, 42.3, 46.0, 46.4, 48, 65
  • Supports front or rear panel XMC I/O
  • Supports front or rear panel AcroPack I/O
  • ±12V AUX power to XMC site

 

 

What is FPGA Zynq UltraScale+ with MPSoC? - 8401065 (Log in to view the file)
APZU FPGA-based digital I/O modules provide programmable Xilinx® Zynq UltraScale+ MPSoC This paper is a brief overview of some of Acromag’s APZU FPGA Zynq® UltraScale+™ with MPSoC products, as well as the features of AcroPack Zinq UltraScale+, the carrier boards that host AcroPack mezzanine modules. We’ll highlight some of the development tools, the engineering design kit, and...
What are FPGAs and FPGA Applications? | Webcast
FPGAs and Their Use in the Embedded Space What are FPGAs and FPGA Applications in the Embedded Space? Topics in this webcast include: What FPGAs Are Best-suited Applications Coding Methods Processing Types This video is part one of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
How to Use Vivado for FPGA Modifications | Webcast
FPGA Design Modifications Using Vivado & Acromag Tools How to Use Vivado for FPGA Modifications. Topics in this webcast include: Vivado 2019.2 Acromag Example Design Compile Project Produce new MCS file This video is part two of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
What is FPGA Zync UltraScale+? | Webcast
These FPGA modules provide a programmable Xilinx Zynq® UltraScale+™ MPSoC What is FPGA Zync UltraScale+? Acromag’s APZU series modules provide a programmable Xilinx Zynq® UltraScale+™ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. The AcroPack® APZU Mini PCIe FPGA Series is the...
How do FPGA Modules Drive Real-Time Applications? - 8400530
FPGA Modules with an Integrated Processor Drive Real-Time Applications Engineers developing DSP and high speed logic applications are now well-aware that FPGA modules can help them create an integrated, sophisticated solution. The availability of commercial off-the-shelf (COTS) FPGA boards can make these solutions viable and do so in reduced development times. Today, with systems architected...
Migrating from VME to VPX or PCIe: Top 6 Considerations | Webcast
In this webcast several important topics are covered for migrating from VME to VPX or PCIe. This includes the advantages and disadvantages of VME architecture, six key considerations, and an overview of migration to PCIe or VPX (advantages, disadvantages, complexity, performance and cost).   More Resources: What is FPGA Zynq UltraScale+ with MPSoC? | Technology...
APSW-API-LNX (Log in to download the file)
  • Compare

    Embedded Cables

    • Communication Signal Cables
    • Wide assortment of ribbon cables
    Select options
  • Compare

    APSW-API: I/O Function Routines for VxWorks, Windows, Linux

    • Programming interface with function routines for AcroPack modules/carriers.
    • Customizable for other operating systems.
    Select options
  • Compare

    Termination Products

    • DIN rail-mount panels
    • 50 screw terminals on 50-pin connector termination panels
    • 50 screw terminals on SCSI-2 connector termination panels
    • 68 screw terminals on SCSI-3 connector termination panels
    Select options

Additional information

Weight N/A
Dimensions N/A
Part Number

VPX4521-42-20: Vita 42 XMC, air-cooled., VPX4521-42-30: Vita 42 XMC, extended temp., VPX4521-42-50: Vita 42 XMC, conduction-cooled., VPX4521-61-20: Vita 61 XMC, air-cooled., VPX4521-61-30: Vita 61 XMC, extended temp., VPX4521-61-50: Vita 61 XMC, conduction-cooled.

Product Series

AcroPack Series

  • Description

    VPX4521: VPX Carrier Card for AcroPack Modules Description

    The VPX4521 carrier card provides a simple and cost-effective solution for interfacing one XMC and four AcroPack modules to a VPX computer system.

    Connect to the OpenVPX™ compatible system via Data plane for a direct PCIe connection over the VPX backplane. This allows host processors access to a high-performance, low latency interconnect to the AcroPack and XMC modules on the carrier card.

    By inserting AcroPack or XMC industrial I/O and configurable FPGA modules, developers can now leverage hundreds of available functions currently unavailable in a VPX platform.

    These carriers are ideal for high-performance industrial, defense, scientific research, and telephony systems requiring high-speed I/O expansion. The VPX4521 is available in two versions: air-cooled and conduction-cooled.

    The VPX4521 is a member of a 6U OpenVPX mezzanine carrier card family that supports a simple and cost-effective solution for interfacing XMC or AcroPack modules to OpenVPX computer systems.

    Performance Specifications

    NOTE: Specifications below only for VPX4521 carrier. See AcroPack and XMC data sheets for additional specifications.

    PCI Express Bus Compliance

    This device meets or exceeds all written PCI Express Base specifications per revision 3.1.
    Includes a PCIe Gen 3 capable PCIe switch used to expand backplane PCIe port to multiple ports supporting various expansion cards. (AcroPack or mini-PCIe).
    Downstream PCIe switch used to provide four one-lane PCIe ports to AcroPack devices.

    Ease of Use

    A unique carrier and site number is set via slot address. This provides the capability to distinguish a particular AcroPack module from others when multiple instances of the same module are used in a system.

    A standard 14-pin Xilinx JTAG programming header is provided for programming and debugging the FPGA on some AcroPack modules. The JTAG ports of the four AcroPack modules are daisy-chained together.

    There is a separate 14-pin Xilinx JTAG header provided for accessing devices on an XMC mezzanine module.

    General

    Form Factor: 6U VPX bus 6.299” (160mm) x 9.173” (233.0mm).

    Pitch: 1”

    VPX Carrier Interface: Compatible VITA 65 module / slot profiles: MOD6-PER-4F-12.3.1-n Data Plane PCIe Gen1/2/3. FRU EEPROM with temperature monitor.

    Mezzanine Sites: One VITA 42 or VITA 61 XMC module.
    XMC site is PCIe Gen 3 and 8 lanes wide.
    Front panel I/O support for each AcroPack site with 68-pin CHAMP connector (air-cooled only).
    Front panel I/O support for XMC module (air-cooled only).
    Rear I/O support for the AcroPack site with 50 I/O lines.(conduction-cooled only).
    XMC rear I/O compliance is P3w3-X38s+P4w1-X12d+x8d.

    Power Requirements

    Power for Carrier Board Only: +12V (VS1) – 0.9A typical, 1.5A maximum.

    Environmental

    Air-Cooled Operating Temperature: Standard models: 0 to 70°C. Extended temperature models: -40 to 85°C.

    Conduction-Cooled Operating Temperature Range: -40 to 85°C (board must operate in a fully-installed conduction-cooled rack).

    Storage Temperature Range: -55 to 125°C.

    Relative Humidity: 5 to 95% non-condensing.

    Vibration: Designed to comply with VITA 47 Class V1.

    Shock: Designed to comply with VITA 47 Class OS1.

     

  • Features & Benefits

    • OpenVPX™ compatible via expansion plane connection
    • Support upstream/downstream PCIe links
    • Supports use of prXMC single board computers
    • Optional backplane configuration for one 16-lane port, two 8-lane ports, or four 4-lane ports
    • Supports standard VITA 42 and rugged VITA 61 XMC modules on 25W mezzanine site
    • XMC site supports PCIe x8 Gen 3 interface
    • 68 pin HD CHAMP front I/O connectors
    • Supports 78-bits (39 pairs) of XMC I/O to backplane per pattern X38s+X8d+X12d of VITA 46.9
    • Conforms to VITA 42.0, 42.3, 46.0, 46.4, 48, 65
    • Supports front or rear panel XMC I/O
    • Supports front or rear panel AcroPack I/O
    • ±12V AUX power to XMC site

     

     

  • Tech Papers

    What is FPGA Zynq UltraScale+ with MPSoC? - 8401065 (Log in to view the file)
    APZU FPGA-based digital I/O modules provide programmable Xilinx® Zynq UltraScale+ MPSoC This paper is a brief overview of some of Acromag’s APZU FPGA Zynq® UltraScale+™ with MPSoC products, as well as the features of AcroPack Zinq UltraScale+, the carrier boards that host AcroPack mezzanine modules. We’ll highlight some of the development tools, the engineering design kit, and...
    What are FPGAs and FPGA Applications? | Webcast
    FPGAs and Their Use in the Embedded Space What are FPGAs and FPGA Applications in the Embedded Space? Topics in this webcast include: What FPGAs Are Best-suited Applications Coding Methods Processing Types This video is part one of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
    How to Use Vivado for FPGA Modifications | Webcast
    FPGA Design Modifications Using Vivado & Acromag Tools How to Use Vivado for FPGA Modifications. Topics in this webcast include: Vivado 2019.2 Acromag Example Design Compile Project Produce new MCS file This video is part two of a three-part series in collaboration with Vic Myers Associates discussing the use of FPGAs and their applications.  ...
    What is FPGA Zync UltraScale+? | Webcast
    These FPGA modules provide a programmable Xilinx Zynq® UltraScale+™ MPSoC What is FPGA Zync UltraScale+? Acromag’s APZU series modules provide a programmable Xilinx Zynq® UltraScale+™ multiprocessor system on a chip (MPSoC). This MPSoC combines a feature-rich ARM-based processing system and programmable logic in a single device. The AcroPack® APZU Mini PCIe FPGA Series is the...
    How do FPGA Modules Drive Real-Time Applications? - 8400530
    FPGA Modules with an Integrated Processor Drive Real-Time Applications Engineers developing DSP and high speed logic applications are now well-aware that FPGA modules can help them create an integrated, sophisticated solution. The availability of commercial off-the-shelf (COTS) FPGA boards can make these solutions viable and do so in reduced development times. Today, with systems architected...
    Migrating from VME to VPX or PCIe: Top 6 Considerations | Webcast
    In this webcast several important topics are covered for migrating from VME to VPX or PCIe. This includes the advantages and disadvantages of VME architecture, six key considerations, and an overview of migration to PCIe or VPX (advantages, disadvantages, complexity, performance and cost).   More Resources: What is FPGA Zynq UltraScale+ with MPSoC? | Technology...
  • Specs & Data Sheets

  • Software

    APSW-API-LNX (Log in to download the file)
  • Accessories

    • Compare

      Embedded Cables

      • Communication Signal Cables
      • Wide assortment of ribbon cables
      Select options
    • Compare

      APSW-API: I/O Function Routines for VxWorks, Windows, Linux

      • Programming interface with function routines for AcroPack modules/carriers.
      • Customizable for other operating systems.
      Select options
    • Compare

      Termination Products

      • DIN rail-mount panels
      • 50 screw terminals on 50-pin connector termination panels
      • 50 screw terminals on SCSI-2 connector termination panels
      • 68 screw terminals on SCSI-3 connector termination panels
      Select options
  • Additional information

    Additional information

    Weight N/A
    Dimensions N/A
    Part Number

    VPX4521-42-20: Vita 42 XMC, air-cooled., VPX4521-42-30: Vita 42 XMC, extended temp., VPX4521-42-50: Vita 42 XMC, conduction-cooled., VPX4521-61-20: Vita 61 XMC, air-cooled., VPX4521-61-30: Vita 61 XMC, extended temp., VPX4521-61-50: Vita 61 XMC, conduction-cooled.

    Product Series

    AcroPack Series