Answer: The watchdog timer may be triggered internally (via the Trigger Control Register), or externally (via the Trigger input signal). When triggered, the counter/timer register contents is decremented by one each clock cycle, until it reaches 0, upon which a watchdog timer time-out occurs. The current contents of the counter/timer register can be read from the Counter Readback Register. The timer may be clocked via the internal 1MHz, 4MHz, or 8MHz clock, or by an external clock up to 3.5MHz at the counter clock pin. If an external clock is used , the time-out may occur +/- 125ns from the selected clock period, this is due to the asynchronous relationship between the trigger and the selected clock. If an internal clock is used the accuracy is determined by the frequency of the internal clock. On VMEbus based system this derived from the system clock. For PCI, cPCI based sytems a crystal is added to the carrier card.