Since Acromag's SRAM has only a single port, I am concerned that either data will be lost or time delays will be created in my DMA transfer when trying to read and write data to the SRAM at the same time. Is there a way to address this problem?
Answer: There is a simple solution to this issue. By configuring the memory in the FPGA as FIFO memory (you may have to create multiple FIFO blocks depending on your requirements), you can create a temporary buffer for data you are collecting from the I/O ports. Data coming from the field I/O would be passed through this FIFO before being sent to SRAM. A gate function would then be created that would allow field I/O data to be passed out of the FIFO memory into SRAM when no DMA transfers are taking place. Once the DMA transfer is complete, the data stored temporarily in FIFO could then be passed in the SRAM for the next DMA transfer. This allows fast DMA transfers of data from SRAM without concern about delays while waiting for field I/O to be written to the SRAM.
The control line that you would use to control this FIFO gate follows.