I'm trying to re-run Synthesis and Implementation on the "out of the box" Vivado 2014.4 project that came on my XMC-7KA Engineering Design Kit (EDK), part number 9500483C, dated 2015. I'm using the same version of Vivado (no IP upgrades, etc), with the same synth_7A200 and impl_7A200 design run properties, but my result is failing timing.
Also noted, when the project was initial opened, it reported "Synthesis is out of Date" due to the design file AXM_D0xv1_0.vhd being changed (I did not change it).
I have gotten it to implement with passing timing by choosing the "Performance Explore" strategy (versus the Vivado defaults the project came with). I'm just worried I may not be starting with a good baseline. Would you recommend generating a bit file and loading it to the hardware?
My ultimate goal is to modify the base design by adding another DDR3 AXI4 master and another PCIe AXI slave, while at the same time removing the Aurora and P16 functions. Again, I just want to know I can successfully regenerate the original EDK version to know I have a valid baseline.
Appreciate any insight.