VPX 6U Carrier Cards Host XMC & AcroPack mPCIe I/O Modules for Maximum Flexibility: Video
Acromag VPX4520 and VPX4521 VPX 6U carrier cards provide maximum flexibility for interfacing one XMC and four mini-PCIe or AcroPack I/O modules to a VPX computer system. The XMC module site can host a network communication, FPGA, GPU, or other I/O signal processor card. The four AcroPack slots provide a rugged PCIe mini card interface for a mix of analog, digital, serial, and other I/O functions.
Click on the video below to learn more about the VPX4520 and VPX4521 in brief.
Connect to the OpenVPX™ compatible system via the VPX4520 Expansion plane for a direct PCIe connection over the VPX backplane. This subsequently allows host processors access to high-performance, low latency interconnect to the AcroPack and XMC modules on the carrier card.
By inserting AcroPack or XMC industrial I/O, developers can consequently leverage hundreds of available functions currently unavailable in a VPX platform. A PCIe Gen 3 x16 interface connects to the VPX bus either via the data plane or expansion plane.
VPX 6U carrier cards are ideal for high-performance industrial, defense, scientific research, and telephony systems requiring high-speed I/O expansion. Models are also available in air-cooled and conduction-cooled versions. Conduction-cooled versions support extended temperature ranges from -40 to 85°C. Air-cooled models offer front panel access to the I/O, while conduction models route all signals to the rear backplane connectors. In addition, the modules are members of a 6U OpenVPX mezzanine carrier card family; this makes them simple, cost-effective solutions for interfacing XMC or AcroPack modules to OpenVPX computer systems.
Easy to Use
Unique carrier and site numbers are set via slot address. As a result, a particular AcroPack module is distinguishable from others when using multiple instances of the same module in a system.
Some AcroPack modules include a standard 14-pin Xilinx JTAG programming header for programming and debugging the FPGA. The JTAG ports of the four AcroPack modules are daisy-chained together.
Further, there’s a separate 14-pin Xilinx JTAG header provided for accessing devices on an XMC mezzanine module.