Mini PCIe FPGA I/O Modules with Zynq UltraScale+ MPSoC for I/O Processing & Programmable Logic: APZU Video

Acromag’s AcroPack® APZU mini PCIe FPGA series is the smallest, most economical platform to host a Zynq® UltraScale+™ MPSoC FPGA computing device. Designers can increase overall system performance by leveraging the tightly coupled CPU and FPGA computing engines for different signal processing tasks in a very small and cost-effective form factor.

Click on the video below to learn more about the APZU Series in brief.

More About APZU Mini PCIe FPGA I/O Modules

AcroPack modules are a ruggedized version of a mini PCIe card. The modules add a down-facing 100-pin connector to internally route I/O signals through the carrier card, thus securing field connectors. This both eliminates loose cables and increases reliability.

Two dual-core ARM Cortex CPUs (A53 application processor and R5 real-time processor) deliver high-performance computation capability. Additional resources include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. Further, the integrated ASIC-class programmable logic is ideal for compute-intensive tasks and offloading critical applications.

By and large, the true value of Zynq UltraScale+ MPSoC architecture lies in the tight integration of its programmable logic with the processing system. Its high-throughput interface eliminates bottlenecks that plague two-chip ASSP-FPGA solutions and allows designers to easily extend the processing system capabilities. As a result, developers can build custom designs by adding peripherals in the programmable logic. Additionally, developers can increase overall system performance by partitioning hardware and software functions with custom accelerators.

Designed for COTS applications, these FPGA-based digital I/O modules deliver user-customizable I/O in a high-density and rugged form factor. For instance, typical applications include adaptive filtering, sensor fusion, motor control, and image processing.

Acromag’s Engineering Design Kit (EDK) includes an FPGA-generated firmware example design. Consequently, this provides host access to the hardware digital I/O on the APZU module. Furthermore, the example is implemented using the Xilinx Vivado® development environment and offers a starting point from which customers can develop their customized applications.

Increased overall system performance is the result of leveraging the tightly-coupled CPU and FPGA computing engines for different signal processing tasks. Additionally, this can all be achieved with a very small and cost-effective form factor.

Click here for further information on Acromag’s APZU Series.