Features
• Reconfigurable Xilinx Virtex-5 FPGA
• PCIe bus 4-lane Gen 1 interface
• Supports both front and rear I/O connections
• 64 I/O or 32 LVDS lines direct to FPGA via rear (J4)
• Plug-in I/O modules are available for front mezzanine
• FPGA code loads from PCI bus or flash memory
• Two banks of 1Mb x 32-bit dual-ported SRAM
• Two banks of 32Mb x 16-bit DDR2 SDRAM
• Other memory options available (contact factory)
• Supports dual DMA channel data transfer to CPU/bus
• Support for Xilinx ChipScope™ Pro interface
• Conduction-cooled, 0 to 70°C or -40 to 85°C (E versions)