Features
• Altera® EP1K100 FPGA
• Three models available:
• IP-1K110-0024: 24 differential RS485 lines
• IP-1K110-2412: 24 TTL lines and 12 RS485
• IP-1K110-4800: 48 TTL lines
• FPGA programmable via the IP bus
• Local static RAM (64K x 16) under FPGA control
• Programmable PLL-based clock synthesizer
• Supports 8MHz and 32MHz IP bus
• User-programmable interval timer
• Example FPGA design code provided as VHDL
- 8MHz IP bus interface
- Digital I/O control register
- others
• Hardware support for DMA and memory space
• 0 to 70°C (-40 to 85°C E version)
Not recommended for new designs