New Industry Pack digital I/O module is the first to implement a user-configurable Altera® Cyclone^TM II FPGA (the most powerful low-cost FPGA available)

Acromag’s new Industry Pack I/O modules provide a user-configurable FPGA for high-performance processing of custom logic routines and a digital I/O interface supporting a variety of signal types.

Acromag’s new IP-EP200 series Industry Pack I/O modules interface digital I/O signals to a user-configurable Altera® Cyclone^TM II FPGA. The IP-EP200 is the first Industry Pack (IP) module to implement the Cyclone II device, the highest-performing low-cost FPGA on the market, for use in processing user-defined algorithms and custom logic routines. And with JTAG access to the SignalTap® II embedded logic analyzer, engineers can easily monitor internal device operation. Several models are available to accommodate RS-485 differential, TTL, or LVDS digital I/O signals with prices starting at $1000. Extended temperature (-40 to 85°C) models are also available.

All units feature Altera’s Cyclone II EP2C20 FPGA device with 20K logic elements 240Kb RAM, and 26 (18 x 18) embedded multipliers. One IP-EP200 model provides 48 bi-directional TTL I/O lines, another offers 24 differential RS485 I/O lines, and a third has 24 LVDS I/O lines. The “combo” model pairs 24 TTL with 12 RS485 I/O lines on a single IP module.

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Acromag has just completed an update to the Linux Software Library PCISW-API-LNX. This software support package provides an application programming interface with function routines for CompactPCI, PCI, and PMC Modules. It includes C source code. Acromag's Linux software is available for download at no charge.

This new version adds multi-device support for all PMC modules, support for the new PMC-LX/SX Virtex-4 FPGA I/O products, and new firmware files for PMC-AX FPGA Analog I/O modules.

See Acromag at the Real-Time & Embedded Computing Conference which is designed for those developing computer systems and time-critical applications serving multiple industries; data communication and telephony, military and aerospace, industrial control, instrumentation, consumer electronics, image processing, process control, medical instrumentation, vehicular control and maintenance, embedded appliances and more.

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January 25, 2007 - San Jose, CA

Question: I have looked at many different FPGA boards offered by Acromag, and in each case the manual talks about the register map of PCIBAR2. Is that the address space the entire SRAM is mapped into? Does this mean that if I write to this SRAM address space the Xilinx chip will route the data into the SRAM? Or in other words, is it true that the PCI chip has no direct access to the SRAM?

Answer: It depends on which FPGA board you are considering.

PMC-DX Series
The PMC-DX SRAM has a single port which is tied to the FPGA so that any data being retrieved from the SRAM must pass through the FPGA. The example code (the example code and the Code in the FLASH memory is identical) is configured to give you access to the memory via the FPGA (PCIbar2+100000H to 1FFFFFH). Most customers expand on this code by adding blocks of FIFO memory within the FPGA to buffer data going into and out of the SRAM. As with all of our example code, it can be modified or removed as you see fit.

PMC-AX, PMC-CX, PMC-LX and PMC-SX Series
A 256K x 36-bit Dual Port synchronous SRAM (DP-SRAM) is provided on the PMC-AX, PMC-CX, PMC-LX, and PMC-SX boards. One port of the SRAM connects directly to the local bus to allow for PCI access. The remaining port connects directly with the FPGA. This design allows the user to maximize data throughput between the field I/O and the controlling processor.

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